High level test methodologies for complex digital systems

This project aims to facilitate test of digital electronic devices for fabrication faults. This is important to keep the quality of components at a high level and then to make products robust. The complex circuits used for embedded systems, for example a Network on Chip architecture, are difficult to test if traditional methods have to be used. If fault models at high level of abstraction can be used, development of test methods will be less complex. More results are needed to make test methods at high level of abstraction powerful. The research in this project aims to take the test methods at high level of abstraction further on.

This project includes development of fault models and test pattern generations methods for behavior level of abstraction and higher. Such methods are more complex than methods at the logic level. At logic level, the stuck at fault model is a well established model. The picture shows a simple NAND-gate that has a break in a wire. At logic level this fault appears at a stuck at fault on an input to the gate. For this simple functionality a behavior level description can look as the VHDL code shown in the picture. At this level of abstraction, this fault appears as the variable in1 is constant one. For this simple device it is easy to see how the physical fault appear at higher levels of abstraction. For more complex systems, there is a need of research for fault models at high levels of abstractions. Such fault models need to be accurate enough to cover most of the physical faults that are not very unlikely to occur. When IP cores are used, especially soft, fault models at higher levels are particular useful.

Publications

T. Bengtsson, Shashi Kumar, A Survey of High Level Test Methodologies, Technical Report, Dec. 2004.

Project Members

Tomas Bengtsson, Ph.D. student, ING Jönköping

Shashi Kumar, Professor, ING Jönköping

Petru Eles, Professor, IDA Linköping University

Funding

Internal